Bottom Board (Roxy)
The bottom board features the main CPU, FLASH, SRAM, address decoding and device selection logic. Below contains the various board revisions that have been released.
Version 2.0 (In development)
Moving toward a larger memory map with the use of the CPU INST pin. 1MB of address space is available for both instructions and data.
1MB FLASH memory upgrade.
512k SRAM memory upgrade.
Relocation of memory-mapped I/O.
Change in discrete logic to allow FLASH to be accessed as both instruction and data memory (INST override), must be controlled on software.
Begin defining actual user interface.
Version 1.2 (Current)
Some minor updates to the board to make it more functional and efficient.
Fixed some wiring errors in the discrete logic and CPU.
Moved to smaller and cheaper address latches.
Board shrunk some due to smaller latches.
Added WE jumper to flash memory so in-circuit FLASH programming would work correctly.
Works very closely with Top Board V1.1 (all components sandwiched between the two boards).
Since all components are between the two boards, part placement had to be very closely monitored. One issue still exists with the serial port connector making contact with the top of the SRAM chip.
More Images (with V1.1 top board)
*Files created in Cadsoft Eagle Layout Editor, free version. Files may be used with permission as long as no profit is made from them.
Version 1.1
Instead of using the untested 16bit address latch in V1.0, it was decided to go back to the two larger 8-bit latches which had been tested in the wirewrap prototype. Other passive components were converted from through-hole to surface-mount. Even though these components were larger, the placement and routing of each part was more optimal, resulting in a smaller bottom board overall. Works with top board V1.0.
It was overlooked that the 8-bit latches used were rather expensive (at about $8 each). Considering this was nearly the same as the cost of the CPU and more than the memory combined a cheaper solution had to be found. A switch to 74573's solved that problem, but the pinout was different of course. In order to test them adaptors were made to fit into the original sockets.
*Files created in Cadsoft Eagle Layout Editor, free version. Files may be used with permission as long as no profit is made from them.
Version 1.0
The only board I have not created myself. This board did not function, plus placement of components was not optimal. Upon testing, the 16-bit address latch did not function as expected. This board was quickly scrapped in favor of a more optimal and functional design.
Version 0.1 (Wirewrap)
Wirewrap board labeled.
Bottom of wirewrap board. The cool part.
A wirewrap version of the board to test functionality of the concept. All devices were connected via a wirewrap board. All components of top and bottom board were placed on this same board. This board wasn't extremely reliable as memory failures occurred often and it required much babysitting to keep it operational for software development. Thus I worked rather quickly to push out V1.0 to alleviate the problems of the wirewrap board (actually I did schematic entry and passed the board layout to another person)..
